The present invention relates to semiconductor devices and methods for their manufacture. More particularly, the present invention relates to semiconductor devices having a structure and method that results in better control over the resistance properties.
The use of doped silicate glass as an interlayer insulator dielectric is known. When so used, the doped silicate glass layer physically and electrically isolates adjacent layers of the IC wafer. For example, in a typical IC, this interlayer dielectric may be pre-metal or between polysilicon layers.
In the prior art, borophosphosilicate glass (BPSG), which is typically formed via a conventional chemical vapor deposition (CVD) process, and plasma-enhanced borophosphosilicate glass (PEBPSG), which is formed using a plasma-enhanced CVD process, have been widely used as the doped silicate glass insulator material. One of the salient features of PEBPSG/BPSG is its ability to flow and planarize at elevated temperatures (e.g., above 900xc2x0 C.).
As device geometries become smaller and thermal budgets (i.e., the amount of heat the IC can be exposed to) for the fabrication of a particular IC device become more stringent, however, the high temperature requirement of PEBPSG/BPSG proves to be a liability. This is because the PEBPSG/BPSG material does not achieve adequate gap-fill, i.e., the filling of gaps and trenches in the wafer surface, and acceptable planarization characteristics at lower annealing temperatures and/or for submicron geometries.
There is also a prior art ozone-TEOS (tetraethylorthosilicate) process, which produces BPSG with the capability of flowing at lower temperatures (referred to herein as borophospho-tetraethylorthosilicate TEOS glass or BPTEOS). This ozone-TEOS process will be described in greater detail later herein. Because of the lower annealing temperature of BPTEOS, this process is particularly desirable for modern high density, low thermal budget devices. BPTEOS films have, however, certain disadvantages that potentially render them unsuitable for use with certain classes of IC devices.
It has been found that the use of BPTEOS insulating film renders the gate oxide regions of certain MOS devices, such as static random access memory (SRAM) devices, vulnerable to hot carrier degradation. This hot carrier degradation problem is discussed in detail in the existing literature, particularly in U.S. Pat. No. 5,290,727.
It is also known that when BPTEOS is used as an interlayer insulator material, its relative porosity exposes underlying regions to contamination from environmental contaminants such as chemicals or various gases (e.g., hydrogen) used in the back-end processes. The diffusion of contaminants into the underlying regions potentially affects the electrical behaviors of these affected underlying regions. This contamination problem is particularly detrimental to underlying polysilicon load resistor regions, i.e., underlying regions of the polysilicon layer that act as resistors. When contaminated, the resistance values of the polysilicon load resistors may increase or decrease, or even fluctuate beyond their specified values, possibly to the point of causing the affected device to generate erroneous results or even rendering the device completely inoperable.
In view of the foregoing, what is desired is a method and apparatus for protecting the resistance value of polysilicon load resistors from contamination-induced variations in IC devices.
The invention relates, in one embodiment, to a method of manufacturing a semiconductor device, which includes the steps of providing a substrate and forming an oxide layer above the substrate. Further, there are included the steps of forming as a first dielectric layer a silicon-rich layer above the oxide layer, and forming a second dielectric layer above the silicon-rich dielectric layer. In one embodiment, the oxide layer is formed of TEOS.
In yet another embodiment, the invention relates to a semiconductor device having a controlled resistance value within a predetermined range. The semiconductor device includes a substrate and an oxide layer provided above the substrate. There is also included a first dielectric layer that is silicon-rich above the oxide layer. There is further included a second dielectric layer above the silicon-rich layer. Together, the oxide layer and the silicon-rich first dielectric layer form a barrier to substantially protect the underlying substrate from contamination.